Wafer Chip Scale Package (CSP) Inspection

Chip scale packages (CSPs) allow for integration of greater functionality in a much smaller package. Today’s consumer devices require smaller and more powerful CSPs, with thinner materials and more complex layouts. As wafer packaging processes become more difficult and involved, the potential for chip package quality failures is a greater concern. Minimize quality risks in wafer level chip scale packages with Sonix solutions.

Chip Scale Package Inspection with Sonix

Sonix has the expertise to help you image specific interfaces of interest within the chip scale package, efficiently gathering the most useful data so you can maintain the multi-chip package throughput you need. With high resolution imaging of planar defects of less than 0.1 micron, Sonix systems identify and characterize:

CSP Defects Sonix Identifies:

• Non-bonded interfaces
• Die tilt or cupping
• Interlaminate disbonding
• Porous or insufficient die attach
• Die cracks
• Molding compound voids and delaminations
• Chip package cracks
• Delamination within the substrate